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HV746 Dual High Speed 75V 2.5A Ultrasound Pulser
Features
HVCMOS technology for high performance High density integration ultrasound transmitter 0 to 75V output voltage 2.5A source and sink current in PW mode 800mA source and sink current in CW mode Up to 20MHz operation frequency Matched delay times 1.2V to 5.0V CMOS logic interface Over temperature sensing Under voltage protections Built-in output drain bleed resistors
General Description
The Supertex HV746 is a dual-channel monolithic high voltage high-speed pulse generator. It is designed for portable medical ultrasound applications. This high voltage and high-speed integrated circuit can also be used for other piezoelectric, capacitive or MEMS sensor in ultrasonic nondestructive detection and sonar ranger applications. The HV746 consists of controller logic interface circuit, level translators, MOSFET gate drives and high current power Pchannel and N-channel MOSFETs as the output stage for each channel. A 2-bit mode control is provided that allows the maximum output current to be reduced for power saving. The output stages of each channel are designed to provide peak output currents over 3.6A for pulsing, when in mode 4, with up to 75V swings. When in mode 1, all the output stages drop the peak current to 800mA for low-voltage CW mode operation to save power consumption of the IC. The P and N type of power FETs gate drivers are supplied by two floating 9.0VDC power supplies reference to VPP and VNN. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier.
Applications
Portable medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound equipment Pulse waveform generator
Typical Application Circuit
+1.8 to 3.3V C1 VLL OT P EN MC0 MC1 PIN1 +1.8 to 3.3V Logic EN_P WR +9V C2 VDD SU B RGND RP1 C3 VSUB +75V VPP -9V C4 VPF VPP 0 to +75V C5
Level Translator
P-Driver
TXP1 D1 HVOUT1
NIN1
Level Translator
TXN1
D2
N-Driver
RN1 X1 1 of 2 Channels RGND VNN C7 C6 VNN +9V 0 to -75V
GREF
VSS
HV746
VNF
HV746
Ordering Information
Package Options Device HV746 48-Lead QFN 7x7mm body, 1.0mm height (max), 0.5mm pitch HV746K6-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VSS, Power supply reference VLL, Positive logic supply VDD, Positive logic and level translator supply (VPP -VPF) Positive floating gate drive supply (VNF- VNN) Negative gate floating drive supply (VPP-VNN) Differential high voltage supply VPP, High voltage positive supply VNN, High voltage negative supply All logic input PIN, NIN and EN pin voltages OTP, over temperature protection output (VSUB - VSS) Substrate to VSS voltage difference (VPP -TXPX) VPP to TXPX voltage difference (VSUB- TXPX) Substrate to TXPX voltage difference (TXNX-VNN ) TXNX to VNN voltage difference dVPP/dt, HV positive supply maximum slew rate dVNN/dt, HV negative supply maximum slew rate Storage temperature Thermal resistance, JA (4-layer,1oz, 4x3in. 9-via PCB) Thermal resistance, JC Value 0V -0.5V to +7V -0.5V to +14V -0.5V to +14V -0.5V to +14V +180V -0.5V to +95V +0.5V to -95V -0.5V to +7.0V -0.5V to +7.0V +180V +180V +180V +180V 25V/s 25V/s -65C to 150C 29C/W 0.5C/W
Pin Configuration
48
1
48-Lead QFN (K6)
(Top View)
Package Marking
HV746K6 LLLLLLLLL YYWW AAA CCC
L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging
48-Lead QFN (K6)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Power-Up Sequence
1 2 3 4 5 6 VSUB VLL with logic signal low VDD (VPP -VPF) and (VNF-VNN) VPP and VNN Logic control signals go to hi
Power-Down Sequence
1 2 3 4 5 6 Logic control signals go to low VPP and VNN (VPP -VPF) and (VNF-VNN) VDD VLL VSUB
2
HV746
Operating Supply Voltages and Current (2 Channel Active)
(Operating conditions, unless otherwise specified, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25C)
Sym VLL VDD VPF VNF VSUB VPP VNN SRMAX ILL IDDQ IDDEN IDDEN IDDENCW IPPQ IPPEN IPPENCW INNQ INNEN INNENCW IPFQ IPFEN IPFENCW INFQ INFEN INFENCW
Parameter Logic voltage reference Internal voltage supply P-FET gate driver supply N-FET gate drive supply IC substrate voltage Positive HV supply Negative HV supply Slew rate limit of VPP, VNN VLL Current EN = Low VDD Current EN = Low VDD Current EN = High VDD Current MODE = 4 VDD Current MODE = 1 VPP Current EN = Low VPP Current MODE = 4 VPP Current MODE = 1 VNN Current EN = Low VNN Current MODE = 4 VNN Current MODE = 1 VPF Current EN = Low VPF Current MODE = 4 VPF Current MODE = 1 VNF Current EN = Low VNF Current MODE = 4 VNF Current MODE = 1
Min 1.2 8.0 (VPP-12)
Typ 1.8 to 3.3 9.0 (VPP-9.0)
Max 5.0 12 (VPP-8.0)
Units Conditions V V V V V V V V/ms A A mA mA A mA A mA A mA A mA ----Floating driver voltage supplies. Must connect to the most positive potential of the IC. ----Built-in slew rate detection protection. ----f = 0MHz f = 5.0MHz, continuous, no loads --f = 5.0MHz, continuous, no loads --f = 5.0MHz, continuous, no loads --f = 5.0MHz, continuous, no loads --f = 5.0MHz, continuous, no loads
(VNN+8.0) (VNN+9.0) (VNN+12) VDD 0 -75 VPP 35 15 0.75 0.75 2.0 10 250 170 15 250 170 10 50 12 20 25 12 +75 +75 0 25 120 2.0 25 30 25 30 -
Under Voltage and Over Temperature Protection
Sym VPULL_UP VUVDD VUVLL VUVVF VOL_OTP IOTP TOTP THYS Parameter Open drain pull-up voltage VDD threshold VLL threshold VPF, VNF threshold OTP flag output low voltage Max. open drain output current Over temperature threshold OTP output reset hysteresis Min 4.5 0.8 4.5 95 Typ 0.9 1.0 110 7.0 Max 5.0 6.0 1.0 6.0 1.0 125 Units Conditions V V V V V mA C C --------VLL= 3.3V, OTP = Active, IPULL-UP= 1.0mA VLL= 3.3V, OTP = Active, IPULL-UP= 1.0mA If over temperature occurs, OTP low and all TX outputs will be HiZ.
3
HV746
DC Electrical Characteristics
Sym IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance
(Operating conditions, unless otherwise specified, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25C)
Output P-Channel MOSFET, TXP (Mode 4)
Min 2.5 Typ 3.6 4.0 200 Max Units Conditions A pF --ISD = 100mA VDS = 25V, f = 1.0MHz
Output N-Channel MOSFET, TXN (Mode 4)
Sym IOUT RON COSS Parameter Output saturation current Channel resistance Output capacitance Min 2.5 Typ 3.6 3.75 80 Max Units Conditions A pF --ISD = 100mA VDS = 25V, f = 1.0MHz
MOSFET Drain Bleed Resistor
Sym RP/N1~4 PRO Parameter Output bleed resistance Bleed resistors power limit Min 5.0 Typ 7.5 Max 10 80 Units Conditions k mW -----
Logic Inputs
Sym VIH VIL IIH IIL CIN Parameter Input logic high voltage Input logic low voltage Input logic high current Input logic low current Input logic capacitance Min (VLL- 0.4) 0 -10 Typ Max VLL 0.4 10 10 Units Conditions V V A A pF -----------
AC Electrical Characteristics
(Operating conditions, unless otherwise specified, VSS= 0V, VLL= +3.3V, VDD= +9.0V, VPP-VPF= +9.0V, VNN- VNF= -9.0V, VPP= +75V, VNN= -75V,TA= 25C)
Sym tr tf fOUT HD2 tEN tDIS tdr tdf tdm tdelay tJ
Parameter Output rise time Output fall time Output frequency range Second harmonic distortion Enable time Disable time Delay time on inputs rise Delay time on inputs fall Delay on mode change |tdr - tdf| delay time matching Delay jitter on rise or fall
Min -
Typ 18 18 -28 180 2.8 22 22 2.5 2.0 15
Max 20 500 10 10 -
Units Conditions ns ns MHz dB s s ns ns ns ns ns VPP/VNN= +/-25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5k load 100 resistor load 330pF//2.5k load
4
HV746
Switching Time Diagram
NINx
50% PINx tdr 90%
50% tdf VPP
Output
10% tr
tf 0 10%
VNN
90%
Drive Mode Control Table
Mode 1 2 3 4 MC1 0 0 1 1 MC0 0 1 0 1 ISC
(A)
RON P
()
RON N
()
0.82 1.16 1.94 3.6
18 13 7.5 4.0
17 12 7.0 3.8
Note: 1. VPP/VNN= +/-75V, VDD= (VPP -VPF) = (VNF-VNN) = +9.0V 2. ISC is current into 1.0 to GND 3. Ron calculated from VOUT into 100 load
Truth Table (Mode = X)
Logic Inputs EN 1 1 1 1 0
Note: * Not allowed, may damage IC.
Output NINX 0 0 1 1 X TXPX OFF ON OFF ON* OFF TXNX OFF OFF ON ON* OFF
PINX 0 1 0 1 X
5
HV746
Pin Description
Pin # 1 2 3 4 5, 6, 7, 8 9 10 11 12 13 14 15 16 17 18,19, 20 21, 22, 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38, 39, 40 41, 42, 43 44 45 46 47 48 Name VDD VSS PIN1 NIN1 N/C PIN2 NIN2 VSS VDD OTP MC1 MC0 VSUB VPF VPP VNN VNF VSUB RGND TXN2 TXP2 TXN1 TXP1 RGND VSUB VNF VNN VPP VPF VSUB EN GREF VLL Function Positive internal voltage supply (+9.0V). Power supply return (0V). Input logic control of high voltage output P-FET of channel 1, Hi = ON, Low = OFF. Input logic control of high voltage output N-FET of channel 1, Hi = ON, Low = OFF. Not Connected Input logic control of high voltage output P-FET of channel 2, Hi = ON, Low = OFF. Input logic control of high voltage output N-FET of channel 2, Hi = ON, Low = OFF. Power supply return (0V). Positive internal voltage supply (+9.0V). Over temperature protection output, open N-FET drain, active low if IC temperature >110C. Output current mode control pins, see Drive Mode Control Table. Substrate of the IC, All VSUB pins must connect to the most positive potential of the IC externally. P-FET gate driver floating power supply, (VPP- VPF) = +9.0V. Positive high voltage power supply (+75V). Negative high voltage power supply (-75V). N-FET gate driver floating power supply, (VNF- VNN) = +9.0V. Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally. Bleed resistors common return ground. Output N-FET drain (open drain output) for channel 2. Output P-FET drain (open drain output) for channel 2. Output N-FET drain (open drain output) for channel 1. Output P-FET drain (open drain output) for channel 1. Bleed resistors common return ground. Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally. N-FET gate driver floating power supply, (VNF- VNN) = +9.0V. Negative high voltage power supply (-75V). Positive high voltage power supply (+75V). P-FET gate driver floating power supply, (VPP- VPF) = +9.0V. Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally. Chip power enable Hi = ON, Low = OFF. Logic low reference, logic ground (0V). Logic Hi voltage reference input (+3.3V). Substrate bottom is internally connected to the central thermal pad on the bottom of package. It must be connected to VSUB, the most positive potential of the IC externally.
Thermal Pad (VSUB)
6
HV746
48-Lead QFN Package Outline (K6)
7x7mm body, 1.0mm height (max), 0.50mm pitch
48 D D2 48 Note 1 (Index Area D/2 x E/2) 1 Note 1 (Index Area D/2 x E/2) E b e
1
E2
View B
Top View
Bottom View
Note 3
A A1
A3 Seating Plane L1 Note 2
L
Side View
View B
Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square.
Symbol MIN Dimension (mm) NOM MAX
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D 6.85 7.00 7.15
D2 2.25 4.70 5.25
E 6.85 7.00 7.15
E2 2.25 4.70 5.25
e 0.50 BSC
L 0.30 0.40 0.50
L1 0.00 0.15
0O 14O
JEDEC Registration MO-220, Variation VKKD-2, Issue K, June 2006. Drawings are not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV746 A092707 7

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